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TDA7410ND
Signal processor for car radio applications
Features

Device Includes Audio Processor, Stereo Decoder And Noiseblanker No External Components Required Fully Programmable Via I2C Bus Softstep Volume and Bass Low Distortion Low Noise SO20 Package Switched-capacitors design technique allows the users to enjoy these features without external components or adjustments. This means higher quality and reliability as well as overall cost saving. The device is fully programmable by I2C bus interface allowing customization of key device parameters, especially filter characteristics.. SO20
Description
TDA7410ND is a signal processor specifically designed for car radio applications. The device includes a complete audioprocessor and a stereo decoder with noiseblanker, stereoblend and all signal processing functions for car radio system. Table 1. Device summary
Part number TDA7410ND TDA7410NDTR
Package SO20 SO20
Packing Tube Tape and reel
February 2007
Rev 2
1/34
www.st.com 1
Contents
TDA7410ND
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 4
Audio Processor Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Description of the audioprocessor part . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Input matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AutoZero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Softstep Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Speaker Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stereodecoder part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Noise blanker part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Description of stereodecoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Deemphasis and highcut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLL and pilot tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Fieldstrength control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LEVEL input and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Stereoblend control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/34
TDA7410ND
Contents
6.8
Highcut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Functional description of the noiseblanker . . . . . . . . . . . . . . . . . . . . . 22
7.1 7.2 7.3 7.4 7.5 Trigger path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Automatic noise controlled threshold adjustment (ATC) . . . . . . . . . . . . . . 22 Automatic threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Over deviation detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 8.2 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
List of tables
TDA7410ND
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Stereodecoder electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Noise blanker electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Subaddress (Receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Source selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Volume Control (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Speaker attenuation (2, 3, 4, 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Treble / Level gain (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Stereodecoder adjustment (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Noise blanker adjustment (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Fieldstrength Control (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Test (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bass (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Softstep Control (12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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TDA7410ND
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Soft Step Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bass normal and DC mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Treble Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Vn timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trigger Threshold vs. VPEAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Deviation Controlled Trigger Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Fieldstrength Controlled Trigger Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block diagram of the stereodecoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Internal stereoblend characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Relation between internal and external LEVEL voltage and setup of Stereoblend . . . . . . 21 Highcut characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block diagram of the noiseblander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO20 Mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Block diagram
TDA7410ND
1
Block diagram
Figure 1. Block diagram
CDL CDG CDR 5 AM CASS_R CASS_L AUX_R AUX_L 8 1 2 6 7 Input Multiplexer Digital Control I2C Bus 12 SCL 13 SDA Mute Volume Bass & Loudness Treble 4 3 Mute 11 OutLR OutLF OutRR OutRF 17 Out_LR 19 Out_LF 16 18 Out_RR Out_RF
MPX
9
80kHz LP
Demodulator & Stereo Blend & Stereo Adjust
25kHz LP
S&H
High Cut Control
PLL & VDD 15 Supply 14 GND 20 CREF Pilot Detector
Noise Blanker
Pulse Generator
D A 10 LEVEL
6/34
TDA7410ND
Pins description and connection diagram
2
2.1
Pins description and connection diagram
Connection diagram
Figure 2. Connection diagram
CASS_R CASS_L CDR CDG CDL AUX_R AUX_L AM MPX LEVEL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CREF OUT_LF OUT_RF OUT_LR OUT_RR VDD GND SDA SCL MUTE
2.2
Pin description
Table 2.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Type: I = input O = Output I/O = Input/Output S = Supply
Pins list
Pin # CASS_R CASS_L CDR CDG CDL AUX_R AUX_L AM MPX LEVEL MUTE SCL SDA GND VDD OUT_RR OUT_LR OUT_RF OUT_LF CREF Cassette Input Right Cassette Input Left CD Right Channel Input Ground reference CD CD Left Channel Input Aux Input Right Aux Input Left Channel AM input FM Input (MPX) Level Input Stereodecoder Mute I2C Clock Line I2C Data Line Supply Ground Supply Voltage Right Rear Speaker Output Left Rear Speaker Output Right Front Speaker Output Left Front Speaker Output Reference Capacitor Pin Function Type I I I I I I I I I I I I I/O S S O O O O O
7/34
Audio Processor Part
TDA7410ND
3
Audio Processor Part
Input Multiplexer

Quasi-differential CD Cassette stereo and Aux stereo input AM mono and MPX Input gain stage with auto zero function
Volume Control

1dB attenuator Max. gain 32dB Max. attenuation 79dB Softstep function
Treble

2nd order frequency response Fixed center frequency 12.5kHz 7x2dB steps
Bass Control

2nd order frequency response Fixed center frequency 100Hz DC gain programmable 7x 2dB steps Softstep function
Speaker control

4 independent speaker controls (control range 50dB) Speaker mute
Mute functions

Direct mute Mute by I2C
8/34
TDA7410ND
Electrical Specification
4
4.1
Electrical Specification
Absolute maximum ratings
Table 3.
Symbol Rth-j pins VS Tamb Tstg VESD VESD VESD
Absolute maximum ratings
Parameter Thermal resistance junction-pins Operating supply voltage Operating ambient temperature Storage temperature range ESD protection (Human Body Model) ESD protection (Machine Model) ESD protection (Change Device Model) Value 85 10.5 -40 to 85 -55 to 150 2000 200 750 Unit C/W V C C V V V
4.2
Supply
Table 4.
Symbol VDD IDD
Supply
Parameter Supply voltage Supply current VDD = 8.5V Test Condition Min 7.5 15 Typ 8.5 20 Max 10 25 Unit V mA
4.3
Table 5.
Symbol
Electrical characteristics
Electrical characteristics VS = 8.5V; Tamb= 25C; RL= 10k; all gains = 0dB; f = 1kHz; unless otherwise specified
Parameter Test Condition Min. Typ. Max. Unit
Input selector Rin VCL GIN_MIN GIN_MAX GSTEP Input resistance Clipping level Min. input gain Max. input gain Step resolution All single ended inputs CASS, CD, AUX input AM, MPX input 70 100 2 1.4 0 15 1 130 k VRMS VRMS dB dB dB
Differential stereo inputs Rin CMRR Input resistance Common mode rejection ratio Differential VCM=1 VRMS@ 1kHz 70 40 100 50 130 k dB
Volume control
9/34
Electrical Specification Table 5.
Symbol GMAX AMAX ASTEP EA ET VDC Bass control Fc CRANGE ASTEP DCGAIN Treble control CRANGE ASTEP fc Clipping level Step resolution Center frequency fC1 13 1 10 14 2 12.5 Center frequency Control range Step resolution Bass-DC-gain DC = off DC = on fC Q 90 1.3 13 1 -1 3.5 100 1.5 14 2 0 4.4 Max gain Max attenuation Step resolution Attenuation set error Tracking error DC steps Adjacent attenuation steps From 0dB to GMIN 0.1 0.5 G = -20 to +15dB G = -79 to -20dB -4 -83 -0.5
TDA7410ND
Electrical characteristics (continued) VS = 8.5V; Tamb= 25C; RL= 10k; all gains = 0dB; f = 1kHz; unless otherwise specified
Parameter Test Condition Min. Typ. 32 -79 1 0 0 3 2 3 5 -75 1.5 Max. Unit dB dB dB dB dB dB mV mV
110 1.7 15 3 1 5.5
Hz
dB dB dB dB
15 3 15
dB dB kHz
Speaker attenuators AMAX ASTEP Max Attenuation Step Resolution -53 0.5 -50 1 -47 2 dB dB
Audio outputs VCL ROUT RL CL VDC General eNO S/N D SC Output noise Signal to noise ratio Distortion Channel separation left/right BW=20Hz to 20 kHz all gain = 0dB all gain = 0dB flat; Vo=2VRMS VIN=1VRMS; all stages 0dB 80 15 100 0.01 90 0.3 25 V dB % dB Clipping level Output impedance Output load resistance Output load capacitor DC voltage level 4.0 2 10 d = 0.3% 1.8 2 30 100 VRMS k nF V
10/34
TDA7410ND
Description of the audioprocessor part
5
5.1
Description of the audioprocessor part
Input matrix
The input matrix of the TDA7410ND offers several possibilities to adapt the audioprocessor to the desired application (see Figure 1). Into the standard application we have:

CD quasi differential Cassette stereo Phone AM mono Stereodecoder input Input Stage
CD 100K + CDGND 100K
Figure 3.
CASSETTE 100K IN GAIN
PHONE 100K
AM 100K STEREODECODER 100K
D05AU1613
MPX
5.2
AutoZero
In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid that effect a special offset cancellation stage called AutoZero is implemented. To avoid audible clicks the audioprocessor is muted before the volume stage during this time. In some cases, for example if the P is executing a refresh cycle of the I2C bus programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the TDA7410D could be switched in the "Auto Zero Remain" mode (Bit 6 of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment value remains.
11/34
Description of the audioprocessor part
TDA7410ND
5.3
Softstep Volume
When volume level is changed often an audible click appears at the output. The root cause of those clicks could be either a DC offset before the volume stage or the sudden change of the envelope of the audio signal. With the Softstep feature both kinds of clicks could be reduced to a minimum and are no more audible (see Figure 4). Figure 4. Soft Step Timing
VOUT
2dB
1dB
10ms -1dB
Time
-2dB
D97AU635
5.4
Bass
The attenuation is programmable in the bass stage (see Figure 5): Figure 5. Bass control
12/34
TDA7410ND
Description of the audioprocessor part
5.5
DC Mode
In this mode the DC gain is increased by 4.4dB. In addition the programmed center frequency and quality factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors. (see Figure 6): Figure 6. Bass normal and DC mode
5.6
Treble
The attenuation is programmable in the treble stage (see Figure 7): Figure 7. Treble Control
13/34
Description of the audioprocessor part
TDA7410ND
5.7
Speaker Attenuator
Due to practical aspects the steps in the speaker attenuators are not linear over the full range. At attenuations more than 24dB the steps increase from 2dB to 8dB (please see data byte specification).
5.8
Stereodecoder part

No External components necessary PLL with adjustment fully integrated VCO Automatic pilot dependent MONO/STEREO switching Very high suppression of intermodulation and interference Highcut and Stereoblend characteristics programmable in a wide range Internal noiseblanker with threshold controls I2C bus control of all necessary functions
Table 6.
Stereodecoder electrical characteristics VDD = 8.5V, Deemphasis time const = 50s, VMPX = 500mV, In Gain = 6dB, 75kHz deviation, f = 1kHz, Tamb =25C, unless otherwise spificied
Parameter MPX input level Input resistance Minimum input gain Maximum input gain Step resolution Max. channel separation Test Condition Input gain = 3.5dB Min. Typ. 0.5 100 3.5 11 2.5 40 Max. Unit VRMS k dB dB dB dB
Symbol VIN Rin Gain Gmax GSTEP a
Mono/stereo switch VPTHST1 VPTHST0 VPTHMO1 VPTHMO0 PLL f/f Capture Range 0.5 % Pilot threshold voltage For stereo, PTH=1 For stereo, PTH=0 For mono, PTH=1 For mono, PTH=0 10 15 7 10 15 25 12 19 25 35 17 25 mV mV mV mV
Deemphass and highcut HC50 Deemphasis time constant HC75 HC50 Highcut time constant HC75 Stereodecoder-Byte D5=0 VLEVEL >> VHCH Stereodecoder-Byte D5=1 VLEVEL >> VHCH Stereodecoder-Byte D5=0 VLEVEL >> VHCH Stereodecoder-Byte D5=1 VLEVEL >> VHCH 50 75 150 225 s s s s
14/34
TDA7410ND Table 6.
Description of the audioprocessor part
Stereodecoder electrical characteristics (continued) VDD = 8.5V, Deemphasis time const = 50s, VMPX = 500mV, In Gain = 6dB, 75kHz deviation, f = 1kHz, Tamb =25C, unless otherwise spificied
Parameter Test Condition Min. Typ. Max. Unit
Symbol
Stereoblend and highcut control REF5V LGmin LGmax LGstep VSBLmin VSBLmax VSBLstep Groll VHCHmin VHCHmax VHCHstep VHCLmin VHCLmax Internal reference voltage Min. level gain Max. level gain Level gain step resolution Min. voltage for mono Max. voltage for mono Step resolution Roll off compensation Min. voltage for no highcut Max. voltage for no highcut Step resolution Min. voltage for full highcut Max. voltage for full highcut 5 0 10 0.67 33 58 8.4 2.5 42 66 8.4 17 33 V dB dB dB %REF5V %REF5V %REF5V dB %REF5V %REF5V %REF5V %VHCH %VHCH
Carrier and harmonic suppression at the output 19 39 57 76 Pilot signal Subcarrier Subcarrier Subcarrier f = 19kHz f = 38kHz f = 57kHz f = 76kHz 40 65 55 80 dB dB dB dB
ACI - Adjacent channel interference 114 190 Signal Signal f = 114kHz f = 190kHz 80 70 dB dB
15/34
Description of the audioprocessor part
TDA7410ND
5.9
Noise blanker part

Internal highpass filter Programmable trigger threshold Additional circuit for trigger adjustment (deviation, field-strength) Very low offset current during hold time Selectable pulse suppression times
Table 7.
Symbol
Noise blanker electrical characteristics
Parameter Test Condition NBT=111 NBT=110 NBT=101 Min. Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 2.5 0.9(off) 1.2 2.0 2.8 0.9(off) 1.3 1.8 2.3 Max. Unit mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP V V V VOP VOP VOP VOP V V V V
VTH
Trigger threshold(1),(2)
means. with VPEAK=0.9V
NBT=100 NBT=011 NBT=010 NBT=001 NBT=000 NCT=00
VTRNOISE
Noise controlled trigger threshold(3)
means. with VPEAK=1.5V
NCT=01 NCT=10 NCT=11
VMPX = 0mV VRECT Rectifier voltage VMPX = 50mV; f = 150kHz VMPX = 100mV; f = 150kHz OVD=11 VRECT DEV deviation dependent rectifier voltage(4) means. with VMPX=800mV (75kHz dev.) OVD=10 OVD=01 OVD=00 FSC=11 VRECT FS Fieldstrength Controlled Rectifier Voltage(5) means. with VMPX=0mV VLEVEL<1. All thresholds are measured using a pulse with TR = 2 ms, THIGH = 2 ms and TF = 10ms 2. NBT represents the Noiseblanker-Byte D2~D0 for the noise blanker trigger threshold 3. NAT represents the Noiseblanker-Byte D4~D3 for the noise controlled trigger adjustment 4. OVD represents the Noiseblanker-Byte D7~D6 for the over deviation detector 5. FSC represents the Fieldstrength-Byte D1~D0 for the fieldstrength control
16/34
TDA7410ND Figure 8. Vn timing diagram
VIN VOP
Description of the audioprocessor part
DC
D97AU636
TR
THIGH
TF
Time
Figure 9.
Trigger Threshold vs. VPEAK
VTH
260mV(00) 220mV(01) 180mV(10) 140mV(11) MIN. TRIG. THRESHOLD NOISE CONTROLLED TRIG. THRESHOLD 65mV 8 STEPS 30mV VPEAK(V)
0.9V
D97AU648
1.5V
Figure 10. Deviation Controlled Trigger Adjustment
VPEAK (VOP) 00
2.8 2.0
01
10 1.2 0.9 DETECTOR OFF (11)
D97AU649
20
32.5
45
75
DEVIATION(KHz)
17/34
Description of the audioprocessor part Figure 11. Fieldstrength Controlled Trigger Adjustment
VPEAK MONO STEREO
TDA7410ND
3V
2.3V(00) 1.8V(01) 1.3V(10) NOISE ATC_SB OFF (11)
0.9V
noisy signal
D98AU863
good signal
E'
18/34
TDA7410ND
Description of stereodecoder
6
Description of stereodecoder
The stereodecoder part of the TDA7410ND (see Figure 12) contains all functions necessary to demodulate the MPX signal like pilot tone dependent MONO/STEREO switching as well as "stereoblend" and "highcut" functions. Adaptations like programmable input gain, selectable deemphasis time constant and a programmable fieldstrength input allow to use different IF devices.
Figure 12. Block diagram of the stereodecoder
DEMODULATOR INGAIN MPX 100K 3.5 ... 11dB STEP 2.5dB INFILTER LP 80KHz 4.th ORDER - PLOT CANC - ROLL-OFF COMP. - LP 25KHz DEEMPHASIS + HIGHCUT t=50 or 75s
FM_L
FM_R
PLL + PILOT-DET. F19 F38 STEREO NOISE BLANKER SB CONTROL
REF 5V VSBL
HC CONTROL D A
VHCCH VHCCL
LEVEL INPUT LEVEL INTERN LP 2.2KHZ 1.th ORDER GAIN 0..10dB
HOLDN
D05AU1614
LEVEL
6.1
Input stages
The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4th order input filter has a corner frequency of 80kHz and is used to attenuate spikes and noise and acts as an antialiasing filter for the following switch capacitor filters.
6.2
Demodulator
In the demodulator block the left and the right channel are separated from the MPX signal. In this stage also the 19kHz pilot tone is cancelled.
6.3
Deemphasis and highcut
The lowpass filter for the deemphasis allows to choose between a time constant of 50s and 75s (bit D5, Stereodecoder Adjustment byte). The highcut control range will be in both cases tHC = 2*tDeemp. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between tDeemp...3*tDeemp. There by the resolution will remain always 5 bits independently of the absolute voltage range between the VHCH and VHCL values. The highcut function can be switched off by I2C bus (bit D7, Fieldstrength Control byte set to "0").
19/34
Description of stereodecoder
TDA7410ND
6.4
PLL and pilot tone detector
The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilottone threshold VPTHST. Two different thresholds are available. The detector output (signal STEREO, see block diagram) can be checked by reading the status byte of the TDA7410ND via I2C bus.
6.5
Fieldstrength control
The fieldstrength input is used to control the highcut and the stereoblend function. In addition the signal can be also used to control the noiseblanker thresholds.
6.6
LEVEL input and gain
To suppress undesired high frequency modulation on the highcut and stereoblend function the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC lowpass at 53kHz (working as anti-aliasing filter) and a 1st order switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF. The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB).
6.7
Stereoblend control
The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an demodulator compatible analog signal which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit which is the internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50% or 58% of REF5V (see Figure 13, 14). Figure 13. Internal stereoblend characteristics
0 -5 -10 -15 -20 CS [dB] -25 -30 -35 -40 -45 -50
0
1
2
3
4
5
LEVELINTERN [V]
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TDA7410ND
Description of stereodecoder
To adjust the external LEVEL voltage to the internal range two values must be defined: the LEVEL gain LG and VSBL. To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain:
REF5V L G = ---------------------------------------------------------------------------------------------Field strength voltage [ STEREO ]
The gain can be programmed through 4 bits in the "Level Gain" byte. The MONO voltage VMO (0dB channel separation) can be choosen selecting 33, 42, 50 or 58% of REF5V. Figure 14. Relation between internal and external LEVEL voltage and setup of Stereoblend
INTERNAL VOLTAGES REF 5V INTERNAL VOLTAGES LEVEL INTERN REF 5V
SETUP OF VST
SETUP OF VMO
LEVEL INTERN
LEVEL VSBL VSBL
58% 50% 42% 33%
VMO
VST
t FIELDSTRENGHT VOLTAGE
D97AU639
VMO
VST
t FIELDSTRENGHT VOLTAGE
6.8
Highcut Control
The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17 or 33% of VHCH (see Figure 15). Figure 15. Highcut characteristics
LOWPASS TIME CONSTANT
3*Deemp
Deemp
VHCL
D97AU640
VHCH
FIELDSTRENGHT
21/34
Functional description of the noiseblanker
TDA7410ND
7
Functional description of the noiseblanker
In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of the spikes. Therefore the output of the stereodecoder is held at the actual voltage for 40s. In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the triggerstage a pulse former generates the "blanking" pulse. To avoid any crosstalk to the signal path the noiseblanker is supplied by its own biasing circuit.
7.1
Trigger path
The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter has a corner frequency of 140kHz. The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signalpath for 40s. The block diagram of the noiseblanker is given in Figure 16. Figure 16. Block diagram of the noiseblander
MPX
HIGH PASS
RECTIFIER
RECT
+ VTH
MONOFLOP
HOLDN
+
PEAK LOWPASS +
THRESHOLD GENERATOR
ADDITIONAL THRESHOLD CONTROL
D98AU861
7.2
Automatic noise controlled threshold adjustment (ATC)
There are mainly two independent possibilities for programming the trigger threshold: a) b) the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte) the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte, (see Figure 9).
The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is noisy the PEAK voltage increases
22/34
TDA7410ND
Functional description of the noiseblanker
due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see Figure 9).
7.3
Automatic threshold control
Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (Figure 11). In some cases the behaviour of the noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control byte.
7.4
Over deviation detector
If the system is tuned to stations with a high deviation the noiseblanker can trigger on the higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in the output signal, the noiseblanker offers a deviation dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector, see Figure 10).
7.5
Test Mode
During the test mode which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to "1" several internal signals are available at the CASSR pin. During this mode the input resistance of 100kOhm is disconnected from the pin. The internal signals available are shown in the software specification. Figure 17. Application Example
VDD 100nF 100nF CASS_R CASS_R CASS_L CDR 22F CDG 100nF CDL AUX_R AUX_L 100nF CASS_L 100nF CDR CDG CDL CREF OUT_LF OUT_RF OUT_LR OUT_RR 10F
OUT_LF OUT_RF OUT_LR OUT_RR 100nF MPX 100nF AM SDA SCL MUTE LEVEL
TDA7410ND TDA7410D
MPX AM SDA SCL
100nF AUX_R 100nF AUX_L
MUTE LEVEL GND
23/34
I2C bus specification
TDA7410ND
8
8.1
I2C bus specification
Interface protocol
The interface protocol comprises:

a start condition (S) a chip address byte (the LSB determines read/write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P) the max. clock speed is 500kbits/s
Table 8.
S 1 0
Receive mode
001 1 0 R/W ACK X AZ TS AI A3 A2 A1 A0 ACK DATA ACK P
S = Start R/W = "0" -> Receive Mode (Chip could be programmed by P) "1" -> Transmission Mode (Data could be received by P) ACK = Acknowledge P = Stop
TS = Testing mode AZ = Auto zero remain AI = Auto increment Table 9.
S 1 0
Transmission mode
0 0 1 0 0 R/W ACK X X X X ST X X X ACK P
ST = Stereo X = Not Used The transmitted data is automatic updated after each ACK. Transmission can be repeated without new chip address.
8.2
Reset condition
A Power-On-Reset is invoked if the Supply-Voltage is below than 3.5V. After that the following data is written automatically into the registers of all subaddresses: Table 10.
MSB 1 1 1 1 1 1 1
Reset condition
LSB 0
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TDA7410ND Table 11.
MSB X AZ TS AI A3 A2 A1
I2C bus specification Subaddress (Receive mode)
LSB Function A0 AZ Remain Off On 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Test Mode Off On Auto Increment Off On Source Selector Volume Control Speaker Attenuator LF Speaker Attenuator LR Speaker Attenuator RF Speaker Attenuator RR Treble / Level Gain Stereodecoder Adjustment Noiseblanker Adjustment Fieldstrength Control Test Bass Softstep Configuration
0 1
25/34
I2C bus specification Table 12.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7410ND Source selector (0)
LSB D0 Function Source Selector / Bass Source Selector CD Cassette Aux AM Stereo Decoder Mute Not Used Not Used Input Gain 0dB 1dB : 14dB 15dB Not Used
0 0 0 0 1 1 1 1 0 0 : 1 1 x 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Table 13.
MSB D7 D6
Volume Control (1)
LSB Function D5 D4 D3 D2 D1 D0 Gain/Attenuation +0dB +1dB : +31dB -0dB -1dB : -78dB -79dB mute Soft Step on off
0 0 : 0 0 0 : 1 1 1 0 1
0 0 : 0 1 1 : 1 1 1
0 0 : 1 0 0 : 0 0 1
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 1 : 1 0 1 : 0 1 x
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TDA7410ND Table 14.
MSB D7 D6 D5 D4 D3 D2 D1
I2C bus specification Speaker attenuation (2, 3, 4, 5)
LSB D0 Function Speaker Attenuation LF (LR,RF,RR) Attenuation 0dB -1dB : -23dB -25dB -27dB -29dB -31.5dB -34dB -37.5dB -42dB -50dB Speaker Mute Not used
0 0 : 0 0 0 0 0 0 0 0 0 1 x x
0 0 : 1 1 1 1 1 1 1 1 1 x
0 0 : 0 1 1 1 1 1 1 1 1 x
0 0 : 1 0 0 0 0 1 1 1 1 x
0 0 : 1 0 0 1 1 0 0 1 1 x
0 1 : 1 0 1 0 1 0 1 0 1 x
Table 15.
MSB D7 D6
Treble / Level gain (6)
LSB D5 D4 D3 D2 D1 D0 Treble -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB LEVEL Gain 0dB 0.66dB 1.33dB : 10dB Function Treble / Level Gain
0 0 : 0 0 1 1 : 1 1 0 0 0 : 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
27/34
I2C bus specification Table 16.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7410ND Stereodecoder adjustment (7)
LSB D0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Function Stereodecoder Adjustment STD Unmuted STD Muted In-Gain 11dB In-Gain 8.5dB In-Gain 6dB In-Gain 3.5dB Forced MONO MONO/STEREO switch automatically Pilot Threshold HIGH Pilot Threshold LOW Deemphasis Threshold 50s Deemphasis Threshold 75s Blank Time Adj 38s 25.5s 32s 22s
0 0 1 1
0 1 0 1
Table 17.
MSB D7 D6
Noise blanker adjustment (8)
LSB D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Function Noiseblanker Low Threshold 65mV Low Threshold 60mV Low Threshold 55mV Low Threshold 50mV Low Threshold 45mV Low Threshold 40mV Low Threshold 35mV Low Threshold 30mV Noise Controlled Threshold 260mV Noise Controlled Threshold 220mV Noise Controlled Threshold 180mV Noise Controlled Threshold 140mV Noise Blanker OFF Noise Blanker ON Over deviation Adjust 2.8V Over deviation Adjust 2.0V Over deviation Adjust 1.2V Over deviation Adjust OFF
0 0 1 1
0 1 0 1
28/34
TDA7410ND Table 18.
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
I2C bus specification Fieldstrength Control (9)
LSB D0 0 1 0 1 Function Fieldstrength Control NoiseBlanker Field strength Adj 2.3V NoiseBlanker Field strength Adj 1.8V NoiseBlanker Field strength Adj 1.3V NoiseBlanker Field strength Adj OFF VSBL at 33% REF 5V VSBL at 42% REF 5V VSBL at 50% REF 5V VSBL at 58% REF 5V VHCH at 42% REF 5V VHCH at 50% REF 5V VHCH at 58% REF 5V VHCH at 66% REF 5V VHCL at 17% VHCH VHCL at 33% VHCH High cut OFF High cut ON
29/34
I2C bus specification Table 19.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7410ND Test (10)
LSB D0 Function Test Stereodecoder test signal OFF Test signal enabled External Clock Internal Clock Test signal VHCCH Level internal Pilot magnitude VCO control voltage Pilot Threshold HOLDN NB threshold F228 VHCCL VSBL SBPWM TBD PEAK REF5V REF5V5 VBG1.95 VCO OFF ON Audio processor test mode Enabled OFF
0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
30/34
TDA7410ND Table 20.
MSB D7 D6 D5 D4 D3 D2 D1
I2C bus specification Bass (11)
LSB D0 Bass -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB Bass DC Mode DC Gain = 0dB DC Gain = 4.4 dB Bass Softstep On Off Not Used Function Bass
0 0 : 0 0 1 1 : 1 1 0 1 0 1 x x
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
Table 21.
MSB D7
Softstep Control (12)
LSB D6 D5 D4 D3 D2 D1 D0 Function Softstep Control AutoZero Function Off On Soft Step Time 0.84ms 1.68ms 3.36ms 6.72ms Reserved STD Discharge Off On Not Used
0 1 0 0 1 1 1 0 1 x x 1 0 1 0 1
31/34
Package information
TDA7410ND
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. SO20 Mechanical data and package dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
32/34
TDA7410ND
Revision history
10
Revision history
Table 22.
Date 20-Feb-2007 28-Feb-2007
Document revision history
Revision 1 2 Initial release. Corrected typos. Changes
33/34
TDA7410ND
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